Semiconductor structure and manufacturing method thereof

ABSTRACT

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dopping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion. The recessed portion is located between the fin portions. The bottom surface of the recessed portion is lower than the surface of the substrate between the fin portions. The dopping layer is disposed on the sidewall of the fin portions, the surface of the substrate, and the sidewall and the bottom portion of the recessed portion. The dielectric layer is disposed on the dopping layer. The top surface of the dopping layer and the top surface of the dielectric layer are lower than the top surface of each of the fin portions.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of China application serialno. 201710606013.7, filed on Jul. 24, 2017. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of specification.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to a semiconductor structure and a manufacturingmethod thereof, and more particularly, to a semiconductor structurehaving fin portions and a recessed portion, wherein the recessed portionhas a dopping layer, and a manufacturing method thereof.

Description of Related Art

With the rapid development in semiconductor process techniques, toincrease the speed and the performance of devices, the size of theentire circuit device needs to be continuously reduced, and devicedensity needs to be continuously increased. Currently, athree-dimensional multi-gate structure such as a fin field effecttransistor (FinFET) has been developed to replace the planarcomplementary metal-oxide-semiconductor (CMOS) device. The FinFET hasfin portions extended perpendicularly upward from the surface of thesubstrate and a gate disposed in the surrounding the fin portions toprovide better electrical control to the channels of the FinFET.

SUMMARY OF THE INVENTION

The invention provides a semiconductor structure, wherein a doppinglayer is disposed in the recessed portion between the fin portions.

The invention provides a manufacturing method of a semiconductorstructure for manufacturing the semiconductor structure.

The semiconductor structure of the invention includes a substrate, adopping layer, and a dielectric layer. The substrate has a plurality offin portions and at least one recessed portion. The recessed portion islocated between the fin portions. The bottom surface of the recessedportion is lower than the surface of the substrate between the finportions. The dopping layer is disposed on the sidewall of the finportions, the surface of the substrate, and the sidewall and the bottomportion of the recessed portion. The dielectric layer is disposed on thedopping layer. The top surface of the dopping layer and the top surfaceof the dielectric layer are lower than the top surface of each of thefin portions.

In an embodiment of the semiconductor structure of the invention, thedopping layer completely fills the recessed portion.

In an embodiment of the semiconductor structure of the invention, thedopping layer partially fills the recessed portion.

In an embodiment of the semiconductor structure of the invention, thedopping layer includes a first dopping layer of a first conductivitytype and a second dopping layer of a second conductivity type, and thefin portions include at least one first fin portion and at least onesecond fin portion.

In an embodiment of the semiconductor structure of the invention, thefirst dopping layer is disposed on the sidewall of the first finportion, a portion of the surface of the substrate, and a portion of thesidewall and a portion of the bottom portion of the recessed portion,and the second dopping layer is disposed on the sidewall of the secondfin portion, the remaining sidewall and the remaining bottom portion ofthe recessed portion, and the first dopping layer in the recessedportion.

In an embodiment of the semiconductor structure of the invention, thefirst dopping layer and the second dopping layer completely fill therecessed portion.

In an embodiment of the semiconductor structure of the invention, thefirst dopping layer and the second dopping layer partially fill therecessed portion.

In an embodiment of the semiconductor structure of the invention, thefirst dopping layer completely fills the recessed portion.

In an embodiment of the semiconductor structure of the invention, thesubstrate has a first recessed portion and a second recessed portionlocated between the first fin portion and the second fin portion, thefirst dopping layer is disposed on the sidewall of the first finportion, a portion of the surface of the substrate, and the sidewall andthe bottom portion of the first recessed portion, and the second doppinglayer is disposed on the sidewall of the second fin portion, theremaining surface of the substrate, and the sidewall and the bottomportion of the second recessed portion.

In an embodiment of the semiconductor structure of the invention, aconductive layer is further included. The conductive layer is disposedon the dielectric layer and the fin portions exposed by the dielectriclayer, wherein the conductive layer and the recessed portion are atleast partially overlapped.

The manufacturing method of the semiconductor structure of the inventionincludes: providing a substrate, wherein the substrate has a pluralityof fin portions and at least one recessed portion, the recessed portionis located between the fin portions, and the bottom surface of therecessed portion is lower than the surface of the substrate between thefin portions; forming a dopping layer on the sidewall of the finportions, the surface of the substrate, and the sidewall and the bottomportion of the recessed portion; and forming a dielectric layer on thedopping layer. The top surface of the dopping layer and the top surfaceof the dielectric layer are lower than the top surface of each of thefin portions.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the dopping layer completely fills therecessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the dopping layer partially fills therecessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the dopping layer includes a first doppinglayer of a first conductivity type and a second dopping layer of asecond conductivity type, and the fin portions include at least onefirst fin portion and at least one second fin portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the first dopping layer is disposed on thesidewall of the first fin portion, a portion of the surface of thesubstrate, and a portion of the sidewall and a portion of the bottomportion of the recessed portion, and the second dopping layer isdisposed on the sidewall of the second fin portion, the remainingsidewall and the remaining bottom portion of the recessed portion, andthe first dopping layer in the recessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the first dopping layer and the seconddopping layer completely fill the recessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the first dopping layer and the seconddopping layer partially fill the recessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the first dopping layer completely fills therecessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, the substrate has a first recessed portionand a second recessed portion located between the first fin portion andthe second fin portion, the first dopping layer is disposed on thesidewall of the first fin portion, a portion of the surface of thesubstrate, and the sidewall and the bottom portion of the first recessedportion, and the second dopping layer is disposed on the sidewall of thesecond fin portion, the remaining surface of the substrate, and thesidewall and the bottom portion of the second recessed portion.

In an embodiment of the manufacturing method of the semiconductorstructure of the invention, after the dielectric layer is formed, aconductive layer is further formed on the dielectric layer and the finportions exposed by the dielectric layer, and the conductive layer andthe recessed portion are at least partially overlapped.

Based on the above, in the semiconductor structure of the invention, arecessed portion is disposed between the fin portions, and a doppinglayer used for doping the substrate and the fin portions is disposed inthe recessed portion.

In order to make the aforementioned features and advantages of thedisclosure more comprehensible, embodiments accompanied with figures aredescribed in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1D are cross sections of a manufacturing process of asemiconductor structure shown according to the first embodiment of theinvention.

FIG. 2A to FIG. 2F are cross sections of a manufacturing process of asemiconductor structure shown according to the second embodiment of theinvention.

FIG. 3 is a cross section of a semiconductor structure shown accordingto the third embodiment of the invention.

FIG. 4 is a cross section of a semiconductor structure shown accordingto the fourth embodiment of the invention.

FIG. 5 is a cross section of a semiconductor structure shown accordingto the fifth embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1A to FIG. 1D are cross sections of a manufacturing process of asemiconductor structure shown according to the first embodiment of theinvention. First, referring to FIG. 1A, a substrate 100 having finportions 100 a is provided. The fin portions 100 a are, for instance,formed by a patterning process performed on the bulk substrate 100. Inan embodiment, a patterned hard mask layer (not shown) can be firstformed on the substrate 100, and then an anisotropic etching process isperformed by using the patterned hard mask layer as an etch mask toremove a portion of the substrate 100 to form the fin portions 100 a. Inthis case, in a subsequent process, the top surface of the fin portions100 a can keep the patterned hard mask layer, and based on actual need,the patterned hard mask layer is removed from the top surface of the finportions 100 a at the right moment. In FIG. 1A, the number of the finportions 100 a is only exemplary, and the invention is not limited inthis regard. Moreover, based on actual need, the height and width . . .etc. of the fin portions 100 a can be adjusted.

Then, referring to FIG. 1B, a patterned mask layer 102 is formed on thesubstrate 100. The patterned mask layer 102 is, for instance, apatterned photoresist layer. The patterned mask layer 102 exposes atleast one of the fin portions 100 a. In the present embodiment, thepatterned mask layer 102 exposes one fin portion 100 a and thesurrounding substrate 100. In another embodiment, the patterned masklayer 102 may only expose the fin portion 100 a without exposing thesurrounding substrate 100. Next, an etching process is performed byusing the patterned mask layer 102 as a mask to remove the exposed finportion 100 a and a portion of the surrounding substrate 100. Theetching process is, for instance, an anisotropic etching process. In thepresent embodiment, after the exposed fin portion 100 a is removed, arecessed portion 100 b is formed in the substrate 100. The recessedportion 100 b can be used to separate the fin portions 100 a. The bottomsurface of the recessed portion 100 b is lower than the surface of thesubstrate 100 between the fin portions 100 a. The width of the recessedportion 100 b can be controlled by adjusting the region exposed by thepatterned mask layer 102, and the depth of the recessed portion 100 bcan be controlled by adjusting the time of the etching process, and theinvention is not particularly limited in this regard. In the presentembodiment, only one of the fin portions 100 a is removed, but in otherembodiments, more of the fin portions 100 a can be removed based onactual need. In the case where the patterned mask layer 102 only exposesthe fin portion 100 a without exposing the surrounding substrate 100,only the exposed fin portion 100 a is removed, so that the formedrecessed portion 100 b has a width same as the width of the bottom ofthe fin portion 100 a.

Next, referring to FIG. 1C, the patterned mask layer 102 is removed. Atthis point, the substrate 100 has a plurality of fin portions 100 a anda recessed portion 100 b located between the fin portions 100 a. In thepresent embodiment, for a subsequent application, the conductivity typesof a portion of the substrate 100 and a portion of the fin portions 100a need to be adjusted. Therefore, a dopant needs to be provided in aportion of the substrate 100 and the fin portions 100 a. Detaileddescription is provided below.

A dopping layer 104 is formed on the substrate 100. The dopping layer104 is a dielectric layer containing a P-type dopant or an N-typedopant. The dielectric layer is, for instance, an oxide layer, a nitridelayer, or a carbide layer. The dopping layer 104 can be formed by, forinstance, a chemical vapor deposition (CVD) process or an atomic layerdeposition (ALD) process. In the present embodiment, the dopping layer104 is, for instance, borosilicate glass (BSG). The dopping layer 104 isconformally formed on the substrate 104 to cover the entire fin portions100 a and cover the sidewall and the bottom portion of the recessedportion 100 b. Next, a liner 105 is formed on the dopping layer 104. Theliner 105 is, for instance, a nitride layer. The dopping layer 104 canbe conformally formed on the dopping layer 104 by, for instance, a CVDprocess or an ALD process.

Then, referring to FIG.1D, a dielectric layer 106 is formed on thesubstrate 100. The dielectric layer 106 covers the fin portions 100 aand completely fills the recessed portion 100 b. Next, an etch-backprocess is performed to remove a portion of the dopping layer 104, aportion of the liner 105, and a portion of the dielectric layer 106 suchthat the top surfaces of the dopping layer 104, the liner 105, and thedielectric layer 106 are lower than the top surface of the fin portions100 a, i.e., the upper end of the fin portions 100 a is exposed. In thepresent embodiment, the top surfaces of the dopping layer 104, the liner105, and the dielectric layer 106 are coplanar, but the invention is notlimited thereto. Next, an annealing treatment can be performed todiffuse the dopant in the dopping layer 104 into the surroundingsubstrate 100 and the fin portions 100 a. It should be mentioned that,the annealing treatment is not limited to be immediately performed afterthe etch-back process, and can be performed at any suitable time basedon actual need.

After a portion of the dopping layer 104, a portion of the liner 105,and a portion of the dielectric layer 106 are removed, the resultingstructure can be used as the substrate for the manufacture of a finFET.Detailed description is provided below.

A dielectric layer 108 is conformally formed on the surfaces of thedopping layer 104, the liner 105, the dielectric layer 106, and theexposed fin portions 100 a, and a conductive layer 110 is formed on thedielectric layer 108. The dielectric layer 108 is used as the gatedielectric layer of a finFET, and the conductive layer 110 is used asthe gate of the finFET. The forming methods of the dielectric layer 108and the conductive layer 110 are known to those skilled in the art andare not repeated herein. Next, any known finFET process can be furtherperformed. As a result, a finFET can be respectively formed in theregions separated by the recessed region 100 b.

In the present embodiment, the recessed portion 100 b separates theplurality of fin portions 100 a, and the dopping layer 104 is formed onthe sidewall and the bottom portion of the recessed portion 100 b.Moreover, in the present embodiment, after the dielectric layer 108 andthe conductive layer 110 are formed, the conductive layer 110 and therecessed portion 100 b are at least partially overlapped. Moreover, inthe present embodiment, the dopping layer 104 does not completely fillthe recessed portion 100 b, but the invention is not limited thereto. Inother embodiments, the dopping layer 104 can also completely fill therecessed portion 100 b.

FIG. 2A to FIG. 2E are cross section of a manufacturing process of asemiconductor structure shown according to the second embodiment of theinvention. In the present embodiment, the step described in FIG. 2A isperformed after FIG. 1B. First, referring to FIG. 2A, the patterned masklayer 102 is removed after the step of FIG. 1B. At this point, thesubstrate 100 has a plurality of fin portions 100 a and a recessedportion 100 b located between the fin portions 100 a. In the presentembodiment, the recessed portion 100 b can separate the substrate 100into a region 200 a and a region 200 b, wherein the region 200 a and theregion 200 b each have a plurality of fin portions 100 a.

Next, a dopping layer 202 is formed on the substrate 100. In the presentembodiment, the dopping layer 202 is a dielectric layer containing aP-type dopant. The dopping layer 202 and the dopping layer 104 aresimilar in terms of material and forming method, which are not repeatedherein. The dopping layer 202 is conformally formed on the substrate 100to cover all of the fin portions 100 a and cover the sidewall and thebottom portion of the recessed portion 100 b. Next, a liner 203 isformed on the dopping layer 202. The liner 203 and the liner 105 aresimilar in terms of material and forming method, which are not repeatedherein. Then, a mask layer 204 is formed on the substrate 100. In thepresent embodiment, the mask layer 204 not only covers the liner 203 inthe region 200 a, but also covers a portion of the liner 203 in therecessed portion 100 b. Next, an etching process is performed by usingthe mask layer 204 as a mask to remove the liner 203 not covered by themask layer 204 and the dopping layer 202 below the liner 203.

Next, referring to FIG. 2B, the mask layer 204 is removed. Next, adopping layer 206 is formed on the substrate 100. The dopping layer 206is a dielectric layer containing an N-type dopant. The dopping layer 206and the dopping layer 104 are similar in terms of material and formingmethod, which are not repeated herein. The dopping layer 206 isconformally formed on the substrate 100 to cover all of the fin portions102 a in the region 200 b, cover the sidewall and the bottom portion ofthe recessed portion 100 b not covered by the dopping layer 202, andcover the liner 203. In the present embodiment, a dopping layer 202containing a P-type dopant and a dopping layer 206 containing an N-typedopant are formed in the recessed portion 100 b, and the dopping layer202 and the dopping layer 206 only partially fill the recessed portion100 b.

Next, referring to FIG. 2C, a mask layer 207 is formed on the substrate100. In the present embodiment, the mask layer 207 not only covers thedopping layer 206 in the region 200 b, but also covers the dopping layer206 in the recessed portion 100 b. Next, an etching process is performedby using the mask layer 207 as a mask to remove the dopping layer 206not covered by the mask layer 207.

Next, referring to FIG. 2D, the mask layer 207 is removed, and then aliner 209 is formed on the dopping layer 206 and the liner 203. Theliner 209 and the liner 203 are similar in terms of material and formingmethod, which are not repeated herein.

Next, referring to FIG. 2E, the step of FIG. 1D is performed to form adielectric layer 106 on the substrate 100. Next, an etch-back process isperformed to remove a portion of the dopping layer 202, a portion of theliner 203, a portion of the dopping layer 206, a portion of the liner209, and a portion of the dielectric layer 106, such that the topsurfaces of the dopping layer 202, the liner 203, the dopping layer 206,the liner 209, and the dielectric layer 106 are lower than the topsurface of the fin portions 100 a, i.e., the upper end of the finportions 100 a is exposed. In the present embodiment, the top surfacesof the dopping layer 202, the liner 203, the dopping layer 206, theliner 209, and the dielectric layer 106 are coplanar, but the inventionis not limited thereto. Next, an annealing treatment can be performed todiffuse the dopant in the dopping layer 202 and the dopping layer 206into the surrounding substrate 100 and the fin portions 100 a of eachthereof. It should be mentioned that, the annealing treatment is notlimited to be immediately performed after the etch-back process, and canbe performed at any suitable time based on actual need. After the dopantis diffused, the region 200 a can be regarded as a P-type region, andthe region 200 b can be regarded as an N-type region.

Next, referring to FIG. 2F, a dielectric layer 208 a is conformallyformed on the dopping layer 202, the liner 203, the dopping layer 206,the liner 209, the dielectric layer 106, and the surface of the exposedfin portions 100 a in the region 200 a and a conductive layer 210 a isformed on the dielectric layer 208 a, a dielectric layer 208 b isconformally formed on the dopping layer 206, the liner 209, thedielectric layer 106, and the surface of the exposed fin portions 100 ain the region 200 b, and a conductive layer 210 b is formed on thedielectric layer 208 b. In the region 200 a, the dielectric layer 208 ais used as the gate dielectric layer of the P-type finFET, and theconductive layer 210 a is used as the gate of the P-type finFET. In theregion 200 b, the dielectric layer 208 b is used as the gate dielectriclayer of the N-type finFET, and the conductive layer 210 b is used asthe gate of the N-type finFET. The forming methods of the dielectriclayers 208 a and 208 b and the conductive layers 210 a and 210 b areknown to those skilled in the art and are not repeated herein. Next, anyknown finFET process can be further performed. As a result, a P-typefinFET and an N-type finFET can be respectively formed in the regions200 a and 200 b separated by the recessed portion 100 b.

In the present embodiment, the recessed portion 100 b separates theplurality of fin portions 100 a, and the dopping layers 202 and 206 areboth formed in the recessed portion 100 b and partially fill therecessed portion 100 b. Moreover, in the present embodiment, theresulting conductive layers 210 a and 210 b are both partiallyoverlapped with the recessed portion 100 b, but the invention is notlimited thereto. In other embodiments, one of the conductive layers 210a and 210 b can also not be overlapped with the recessed portion 100 b,and the other of the conductive layers 210 a and 210 b can be partiallyor completely overlapped with the recessed portion 100 b. Moreover, inthe present embodiment, a dopping layer containing a P-type dopant isfirst formed, and then a dopping layer containing an N-type dopant isformed, but the invention is not limited thereto. In other embodiments,a dopping layer containing an N-type dopant can be first formed, andthen a dopping layer containing a P-type dopant is formed.

FIG. 3 is a cross section of a semiconductor structure shown accordingto the third embodiment of the invention. Referring to FIG. 3, in thepresent embodiment, the difference from the structure of FIG. 2F is: thedopping layers 202 and 206 formed in the recessed portion 100 bcompletely fill the recessed portion 100 b, and this can be achieved byadjusting the process parameters for forming the dopping layers 202 and206. Similarly, based on actual need, one of the conductive layers 210 aand 210 b can also not be overlapped with the recessed portion 100 b,and the other of the conductive layers 210 a and 210 b can be partiallyoverlapped or completely overlapped with the recessed portion 100 b, andthe forming order of the dopping layer containing a P-type dopant andthe dopping layer containing an N-type dopant is also not limited.

FIG. 4 is a cross section of a semiconductor structure shown accordingto the fourth embodiment of the invention. Referring to FIG. 4, in thepresent embodiment, the difference from the structure of FIG. 2F is: therecessed portion 100 b only has the dopping layer 202, and the doppinglayer 202 completely fills the recessed portion 100 b, and this can beachieved by adjusting the process parameters for forming the doppinglayer 202. In other embodiments, in the case that the dopping layercontaining an N-type dopant is formed before the dopping layercontaining a P-type dopant is formed, the dopping layer containing anN-type dopant can also completely fill the recessed portion 100 b. Basedon actual need, one of the conductive layers 210 a and 210 b can alsonot be overlapped with the recessed portion 100 b, and the other of theconductive layers 210 a and 210 b can be partially or completelyoverlapped with the recessed portion 100 b.

FIG. 5 is a cross section of a semiconductor structure shown accordingto the fifth embodiment of the invention. Referring to FIG. 5, in thepresent embodiment, the difference from the structure of FIG. 2F is: arecessed portion 500 a and a recessed portion 500 bare disposed betweena P-type region (the region 200 a) and an N-type region (the region 200b), the recessed portion 500 a only has the dopping layer 202, therecessed portion 500 b only has the dopping layer 206, the dopping layer202 does not completely fill the recessed portion 500 a, and the doppinglayer 206 does not completely fill the recessed portion 500 b.

In other embodiments, the dopping layer 202 completely fills therecessed portion 500 a and/or the dopping layer 206 completely fills therecessed portion 500 b. Moreover, in the present embodiment, theconductive layer 210 a and the recessed portion 500 a are completelyoverlapped, and the conductive layer 210 b and the recessed portion 500b are completely overlapped, but the invention is not limited thereto.In other embodiments, the conductive layer 210 a can also be partiallyoverlapped with the recessed portion 500 a, and the conductive layer 210b can also be partially overlapped with the recessed portion 500 b.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of ordinary skill in the artthat modifications to the described embodiments may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention is defined by the attached claims not by the abovedetailed descriptions.

1. A semiconductor structure, comprising: a substrate having a pluralityof fin portions and at least one recessed portion, wherein the recessedportion is located between the fin portions and the bottom surface ofthe recessed portion is lower than the surface of the substrate betweenthe fin portions; a dopping layer disposed on a sidewall of the finportions, a surface of the substrate, and a sidewall and a bottomportion of the recessed portion; and a dielectric layer disposed on thedopping layer, wherein a top surface of the dopping layer and a topsurface of the dielectric layer are lower than a top surface of each ofthe fin portions.
 2. The semiconductor structure of claim 1, wherein thedopping layer completely fills the recessed portion.
 3. Thesemiconductor structure of claim 1, wherein the dopping layer partiallyfills the recessed portion.
 4. The semiconductor structure of claim 1,wherein the dopping layer comprises a first dopping layer of a firstconductivity type and second dopping layer of a second conductivitytype, and the fin portions comprise at least one first fin portion andat least one second fin portion.
 5. The semiconductor structure of claim4, wherein the first dopping layer is disposed on a sidewall of thefirst fin portion, a portion of the surface of the substrate, and aportion of the sidewall and a portion of the bottom portion of therecessed portion, and the second dopping layer is disposed on a sidewallof the second fin portion, a remaining sidewall and a remaining bottomportion of the recessed portion, and the first dopping layer in therecessed portion.
 6. The semiconductor structure of claim 5, wherein thefirst dopping layer and the second dopping layer completely fill therecessed portion.
 7. The semiconductor structure of claim 5, wherein thefirst dopping layer and the second dopping layer partially fill therecessed portion.
 8. The semiconductor structure of claim 5, wherein thefirst dopping layer completely fills the recessed portion.
 9. Thesemiconductor structure of claim 4, wherein the substrate has a firstrecessed portion and a second recessed portion located between the firstfin portion and the second fin portion, the first dopping layer isdisposed on a sidewall of the first fin portion, a portion of thesurface of the substrate, and a sidewall and a bottom portion of thefirst recessed portion, and the second dopping layer is disposed on asidewall of the second fin portion, a remaining surface of thesubstrate, and a sidewall and a bottom portion of the second recessedportion.
 10. The semiconductor structure of claim 1, further comprisinga conductive layer disposed on the dielectric layer and the fin portionsexposed by the dielectric layer, wherein the conductive layer and therecessed portion are at least partially overlapped.
 11. A manufacturingmethod of a semiconductor structure, comprising: providing a substratehaving a plurality of fin portions and at least one recessed portion,wherein the recessed portion is located between the fin portions and thebottom surface of the recessed portion is lower than the surface of thesubstrate between the fin portions; forming a dopping layer on asidewall of the fin portions, a surface of the substrate, and a sidewalland a bottom portion of the recessed portion; and forming a dielectriclayer on the dopping layer, wherein a top surface of the dopping layerand a top surface of the dielectric layer are lower than a top surfaceof each of the fin portions.
 12. The manufacturing method of thesemiconductor structure of claim 11, wherein the dopping layercompletely fills the recessed portion.
 13. The manufacturing method ofthe semiconductor structure of claim 11, wherein the dopping layerpartially fills the recessed portion.
 14. The manufacturing method ofthe semiconductor structure of claim 11, wherein the dopping layercomprises a first dopping layer of a first conductivity type and asecond dopping layer of a second conductivity type, and the fin portionscomprise at least one first fin portion and at least one second finportion.
 15. The manufacturing method of the semiconductor structure ofclaim 14, wherein the first dopping layer is disposed on a sidewall ofthe first fin portion, a portion of the surface of the substrate, and aportion of the sidewall and a portion of the bottom portion of therecessed portion, and the second dopping layer is disposed on a sidewallof the second fin portion, a remaining sidewall and a remaining bottomportion of the recessed portion, and the first dopping layer in therecessed portion.
 16. The manufacturing method of the semiconductorstructure of claim 15, wherein the first dopping layer and the seconddopping layer completely fill the recessed portion.
 17. Themanufacturing method of the semiconductor structure of claim 15, whereinthe first dopping layer and the second dopping layer partially fill therecessed portion.
 18. The manufacturing method of the semiconductorstructure of claim 15, wherein the first dopping layer completely fillsthe recessed portion.
 19. The manufacturing method of the semiconductorstructure of claim 14, wherein the substrate has a first recessedportion and a second recessed portion located between the first finportion and the second fin portion, the first dopping layer is disposedon a sidewall of the first fin portion, a portion of the surface of thesubstrate, and a sidewall and a bottom portion of the first recessedportion, and the second dopping layer is disposed on a sidewall of thesecond fin portion, a remaining surface of the substrate, and a sidewalland a bottom portion of the second recessed portion.
 20. Themanufacturing method of the semiconductor structure of claim 11, furthercomprising, after the dielectric layer is formed, forming a conductivelayer on the dielectric layer and the fin portions exposed by thedielectric layer, and the conductive layer and the recessed portion areat least partially overlapped.